The present invention relates to the fabrication of semiconductor integrated circuits (IC's). More particularly, the present invention relates to methods and apparatuses for etching through an IC's layer stack, including an oxide layer, during IC fabrication to create self-aligned contact openings.
In the manufacture of certain semiconductor integrated devices such as metal oxide semiconductor (MOS) transistors, self-aligned contacts offer many advantages. To facilitate discussion, FIGS. 1A and 1B illustrate cross-sectional views of the relevant portion of a layer stack 20, representing the layers formed during the fabrication of a typical semiconductor IC that employs self-aligned contacts. It should be noted that other additional layers above, below, or between the layers shown may be present. Consequently, as the term is used herein, relative positional terms such as "over" or "above" do not necessarily indicate a direct contact between the layers under discussion. Further, not all of the shown layers need necessarily be present and some or all may be substituted by other different layers.
Referring initially to FIG. 1A, there is shown a substrate 22 at the bottom of layer stack 20 (not drawn to scale for ease of illustration). Substrate 22 represents a semiconductor wafer, which is typically formed of silicon. An oxide layer 26, typically comprising SiO.sub.2, is formed above wafer 100 to serve as the gate oxide layer. Above this gate oxide layer 26, there are disposed respective polysilicon gates 28 and 30. Each of these polysilicon gates 28 and 30 is protected by a nitride region of a subsequently deposited nitride layer (Si.sub.3 N.sub.4 or Si.sub.x N.sub.y generally). In FIG. 1A, these nitride regions are shown as nitride regions 32 and 34. Above the gate oxide regions, the polysilicon gates, and the protective nitride regions, there is disposed an oxide layer 40.
To create a contact opening 44 to substrate 22 through oxide layer 40, a layer of photoresist material 42 is deposited and patterned using a conventional photolithography step. After patterning, an initial opening is created in photoresist layer 42 to facilitate subsequent oxide etching. The above-described layers and features, as well as the processes involved in their creation, are well known to those skilled in the art.
FIG. 1B shows the same layer stack 20 of FIG. 1A and its layers. In FIG. 1B, however, a contact opening 44 has been etched through oxide layer 40. Through this contact opening 44, a metal conductor may be formed subsequently to contact the drain and source regions in substrate 22. In the present case, contact opening 44 represents a self-aligned contact, i.e., it performs its contacting function irrespective of whether the sidewalls of the contact opening overlap all or part of the gate stack comprising the gate oxide region, the polysilicon gate, and the protective nitride layer. Since the polysilicon gates themselves are protected by the overlaying nitride material, some misalignment between region D1 between the gate stacks and contact opening 44 may be present without shorting the gate of the resulting transistor to its drain and source. By way of example, sidewall 50 of contact opening 44 is shown overlapping polysilicon gate 28. Nevertheless, the presence of nitride region 32 electrically insulates polysilicon gate 28 from the conductive contact material subsequently deposited into contact opening 44.
The use of self-aligned contacts advantageously permits circuit designers greater flexibility in the placement of the contact openings. In some instances, the use of self-aligned contacts permits circuit designers to pack the gates more closely together since the minimal distance between the gates is not bounded by the dimension of the contact opening (which is limited by, for example, the accuracy of the photolithography and the oxide etch processes).
As can be appreciated by those skilled in the art, the above-described self-aligned contact technique requires that the contact opening, e.g., contact opening 44 of FIG. 1B, be etched without damage to the insulating nitride regions that overlay the polysilicon gates. In other words, it is desirable to etch the contact opening with an oxide etch process that has a high oxide-to-nitride selectivity. In order to ensure an adequate contact area between the subsequently deposited metal layer and the wafer, it is desired that the etch profile be as close to the desired vertical profile as possible with little or no unetched oxide sticking to the nitride sidewall. It is also desirable when etching contact openings to improve the oxide etch rate in order to increase the wafer throughput rate. Additionally, it is also desirable to etch contact openings with a uniform etch rate across the wafer so that dies that are located in the center of the wafer are etched at the same rate as dies that are located at the wafer edge.
In view of the foregoing, what is desired is improved methods and apparatuses for etching self-aligned contacts. Among other advantages, the improved methods and apparatuses preferably maximize the oxide etch rate, the oxide-to-nitride selectivity, and etch uniformity, while improving the etch profile.